1. Field of the Invention
The present invention relates to a method and apparatus for processing a faulty memory, particularly to a method and apparatus for correcting a hard error due to a faulty cell in a dynamic random access memory (RAM).
2. Description of the Prior Art
In general, a memory unit in a data processing system is provided with a function for detecting an error in data read from the memory unit and for correcting the detected error by an error correcting code (ECC). This ECC error detection and correction, however, requires a long time, resulting in a longer memory access time. If the above error detection and correction were executed for all the data read from the memory unit, the processing capability of the data processing system would significantly decrease.
To prevent the above decrease of the processing capability, the read data is first output to a central processing unit (CPU), and the process using the read data is executed before the error detection and correction. This method is useful in cases where a read data error seldom occurs. When an error is detected in the read data, the CPU is stopped in accordance with a memory error signal produced later, the corrected data is written back into the memory, then the read-out operation is rerun.
There are two kinds of errors in data (words) stored in a memory. One is a temporary error, such as a soft error, which can be corrected in the memory by writing back (rewriting) the corrected data. The other is a hard error which cannot be corrected in the memory by rewriting the corrected data. A hard error may occur because of a faulty cell in the memory (e.g., a cell is stuck at "1" or "0"). In the case of a hard error, an error occurs every time that the bad bit is accessed.
There are three prior art methods for coping with hard errors, as follows:
(1) Repairing the faulty cell causing the error when a hard error occurs. This method, however, does not effectively utilize the error detection and correction function. PA1 (2) Executing the above-mentioned ECC error correction every time a hard error occurs. This method, however, lengthens the access time by the time required for each error correction. This in turn slows down the operation of the data processing system, greatly decreasing the processing capability. PA1 (3) Memorizing the memory address of a hard error and carrying out an ECC error correction only when the memorized address is accessed. This method, however, requires a plurality of registers for memorizing the memory address of the hard error and a circuit for detecting coincidence of addresses. Furthermore, according to this method, it is necessary to detect the coincidence of addresses between all addresses input and the addresses in the registers, making the access time longer.
As mentioned above, the prior art systems for dealing with hard errors have disadvantages in that they slow down the operation of the data processing system and thus significantly decrease the processing capability of the data processing system.